/*
 * For loongson7a dc controller dvo1 i2c
 * Use gpio to access ch7034 chip
 * */

#include <pmon.h>
#include <stdio.h>
//#include <target/i2c.h>

#define SCL1	3
#define	SDA1	2

#define SCL0	1
#define	SDA0	0

#define	LOW	0
#define HIGH	1

#define	OUT	0
#define	IN	1

#define CHIP_7034_ADDR	0xea
#define CHIP_9022_ADDR	0x72

#if defined (X800x600)
#define MODE	0
#elif defined(X1366x768) || defined(X1368x768) || defined(X1360x768) || defined(X1365x768) || defined(X1440x900)
#define MODE	1
//#define MODE	2
#elif defined(X1024x768)
//#define MODE	3	//vga
#define MODE	2	//lvds
#endif

#define MODE 2
int tgt_i2cread(int type,unsigned char *addr,int addrlen,unsigned char reg,unsigned char* buf ,int count);
int tgt_i2cwrite(int type,unsigned char *addr,int addrlen,unsigned char reg,unsigned char* buf ,int count);

char i2caddr[]={(unsigned char)0x72};

static unsigned int dc_base = 0;
static unsigned int gpio_val_base = 0;
static unsigned int gpio_dir_base = 0;

unsigned char CH7034_VGA_REG_TABLE2[][131][2] = {
      {	//mtfvga
      //IN 800x600,out 800x600,ch7034,bypassmode vga,mode_idx=1
          { 0x03, 0x04 },//page 4
          { 0x52, 0xC3 },
          { 0x5A, 0x06 },
          { 0x5A, 0x04 },
          { 0x5A, 0x06 },
          { 0x52, 0xC1 },
          { 0x52, 0xC3 },
          { 0x5A, 0x04 },

          { 0x03, 0x00 },//page 1
          { 0x07, 0xD9 },//non
          { 0x08, 0xF1 },//non
          { 0x09, 0x03 },//bit4:scaler power down
          { 0x0A, 0xBE },//bit5:mem power down, bit3:lvds powerdown

	 /* input timing */
          { 0x0B, 0x23 },//h total 0x420 = 1056
          { 0x0C, 0x20 },//h active 0x320 = 800
          { 0x0D, 0x20 },

          { 0x0E, 0x00 },//width + offset
          { 0x0F, 0x28 },//h offset 0x28 = 40
          { 0x10, 0x80 },//h width 0x80 = 128

          { 0x11, 0x12 },//v total 0x274 = 628
          { 0x12, 0x58 },//v active 0x258= 600
          { 0x13, 0x74 },

          { 0x14, 0x00 },//width + offset
          { 0x15, 0x01 },//v offset 1
          { 0x16, 0x04 },//v width 4

          { 0x17, 0x00 },
          { 0x18, 0x00 },//mtf modify 888RGB

          { 0x19, 0xF8 },//freq
          { 0x1A, 0x9B },
          { 0x1B, 0x78 },//0x9b78 = 39800Khz

          { 0x1C, 0x69 },
          { 0x1D, 0x78 },
          { 0x1E, 0x00 },//output is  progressive

	/* output timing */
          { 0x1F, 0x23 },//output h total 0x420 = 1056
          { 0x20, 0x20 },//output h active 0x320 =800
          { 0x21, 0x20 },

          { 0x22, 0x00 },//
          { 0x23, 0x10 },//h offset 16
          { 0x24, 0x60 },//h width 96

          { 0x25, 0x12 },//
          { 0x26, 0x58 },//v active 0x258 = 600
          { 0x27, 0x74 },//v total 0x274 = 628

          { 0x28, 0x00 },
          { 0x29, 0x0A },//v offset 10
          { 0x2A, 0x02 },//v width 2

          { 0x2B, 0x09 },//vga output format:bypass scaler mode ---- 9;through scaler mode 8
          { 0x2C, 0x00 },
          { 0x2D, 0x00 },
          { 0x2E, 0x3D },
          { 0x2F, 0x00 },//??
          { 0x32, 0xC0 },//???
          { 0x36, 0x40 },
          { 0x38, 0x47 },
          { 0x3D, 0x86 },
          { 0x3E, 0x00 },
          { 0x40, 0x0E },
          { 0x4B, 0x40 },//pwm control
          { 0x4C, 0x40 },//lvds output channel order register,bit7:lv_vga_frb
          { 0x4D, 0x80 },
	/* lvds output timing */
          { 0x54, 0x80 },//lvds
          { 0x55, 0x28 },//lvds
          { 0x56, 0x80 },//lvds

          { 0x57, 0x00 },//lvds
          { 0x58, 0x01 },//lvds
          { 0x59, 0x04 },//lvds

          { 0x5A, 0x02 },//non
          { 0x5B, 0xF2 },//non
          { 0x5C, 0xB9 },
          { 0x5D, 0xD6 },
          { 0x5E, 0x54 },
          { 0x60, 0x00 },
          { 0x61, 0x00 },
          { 0x64, 0x2D },
          { 0x68, 0x44 },
          { 0x6A, 0x40 },
          { 0x6B, 0x00 },
          { 0x6C, 0x10 },
          { 0x6D, 0x00 },
          { 0x6E, 0xA0 },
          { 0x70, 0x98 },

          { 0x74, 0x30 },//scaling control
          { 0x75, 0x80 },//scaling control
          { 0x7E, 0x0F },//de and pwm control
          { 0x7F, 0x00 },//test pattern

          { 0x03, 0x01 },//page 2
          { 0x08, 0x05 },
          { 0x09, 0x04 },//diffen register
          { 0x0B, 0x65 },
          { 0x0C, 0x4A },
          { 0x0D, 0x29 },
          { 0x0F, 0x9C },
          { 0x12, 0xD4 },//bit0-5:reserved
          { 0x13, 0x28 },//non
          { 0x14, 0x83 },//non
          { 0x15, 0x00 },//non
          { 0x16, 0x00 },//non
          { 0x1A, 0x6C },//DAC termination control register

          { 0x1B, 0x00 },//non
          { 0x1C, 0x00 },
          { 0x1D, 0x00 },
          { 0x23, 0x63 },
          { 0x24, 0xB4 },
          { 0x28, 0x54 },
          { 0x29, 0x60 },

          { 0x41, 0x60 },//lvds control
          { 0x63, 0x2D },//DE polarity

          { 0x6B, 0x11 },//non
          { 0x6C, 0x06 },

          { 0x03, 0x03 },//page3
          { 0x26, 0x00 },
          { 0x28, 0x08 },//output control:DAC output is VGA, bit3 reserved
          { 0x2A, 0x00 },//output control:HDTV output through scaler

          { 0x03, 0x04 },//page 4
          { 0x10, 0x00 },//non
          { 0x11, 0x9B },//non
          { 0x12, 0x78 },//non
          { 0x13, 0x02 },//non
          { 0x14, 0x88 },//non
          { 0x15, 0x70 },//non
          { 0x20, 0x00 },//non
          { 0x21, 0x00 },//non
          { 0x22, 0x00 },//non
          { 0x23, 0x00 },//non
          { 0x24, 0x00 },//non
          { 0x25, 0x00 },//non
          { 0x26, 0x00 },//non
          { 0x54, 0xC4 },//non
          { 0x55, 0x5B },//non
          { 0x56, 0x4D },//non
          { 0x60, 0x01 },//non

          { 0x61, 0x62 },//non
      },
{      //in 1366x768 out 1366x768,lvds,idx=3 
	{ 0x03, 0x04 },
	{ 0x52, 0xC3 },
	{ 0x5A, 0x06 },
	{ 0x5A, 0x04 },
	{ 0x5A, 0x06 },
	{ 0x52, 0xC1 },
	{ 0x52, 0xC3 },
	{ 0x5A, 0x04 },

	{ 0x03, 0x00 },
	{ 0x07, 0xD1 },//non
	{ 0x08, 0x0F },//non
//	{ 0x09, 0x03 },//bit4: 1 scaler power down
	{ 0x09, 0x13 },//bit4: 1 scaler power down
	{ 0x0A, 0x96 },//set sdram in initialization state
//	{ 0x0A, 0xBE },//set sdram in initialization state, bit3 lvds power down, bit5 mem power down

	/* input timing */
#if 1
	{ 0x0B, 0x3D },//horizontal total pixels 0x700 = 1792
	{ 0x0C, 0x56 },//horizontal active pixels 0x556 = 1366
	{ 0x0D, 0x00 },
#else
	{ 0x0B, 0x23 },//horizontal total pixels 0x420 = 1056
	{ 0x0C, 0x20 },//horizontal active pixels 0x320 = 800
	{ 0x0D, 0x20 },
#endif
	{ 0x0E, 0x00 },//width + offset
	{ 0x0F, 0x46 },//horizontal sync offset 0x46 = 70
	{ 0x10, 0x8F },//horizontal sync pulse width 0x8f = 143
//	{ 0x0E, 0x00 },//width + offset
//	{ 0x0F, 0x28 },//horizontal sync offset 0x28 = 40
//	{ 0x10, 0x80 },//horizontal sync pulse width 0x80 = 128

	{ 0x11, 0x1B },//vertical total pixels 0x31e = 798
	{ 0x12, 0x00 },//vertical active pixels 0x300 = 768
	{ 0x13, 0x1E },
//	{ 0x11, 0x12 },//vertical total pixels 0x274 = 628
//	{ 0x12, 0x58 },//vertical active pixels 0x258 = 600
//	{ 0x13, 0x74 },

	{ 0x14, 0x00 },//width + offset
	{ 0x15, 0x03 },//vertical sync offset 0x3 = 3
	{ 0x16, 0x03 },//vertical sync pulse width 0x3 = 3
//	{ 0x14, 0x00 },//width + offset
//	{ 0x15, 0x01 },//vertical sync offset 0x1 = 1
//	{ 0x16, 0x04 },//vertical sync pulse width 0x4 = 4

//	{ 0x17, 0x00 },
	{ 0x17, 0x20 },
	{ 0x18, 0x00 },//0:rgb888 1:666 2:565
//	{ 0x18, 0x01 },//rgb666

//      { 0x19, 0xF9 },
//      { 0x1A, 0x4D },
//      { 0x1B, 0xFC },//0x14dfc = 85500khz

#if 0
	{ 0x19, 0xF9 },
	{ 0x1A, 0x4F },
//	{ 0x1B, 0x28 },//0x14f28 = 85800khz
//	{ 0x1B, 0x49 },//0x14f49 = 85833khz
	{ 0x1B, 0x2e },//0x14f2e = 85806khz
#else
	{ 0x19, 0xF9 },
	{ 0x1A, 0x11 },
	{ 0x1B, 0x70 },//0x11170 = 70000khz
#endif

	{ 0x1C, 0x69 },
	{ 0x1D, 0x78 },//0x6978 = 27000khz

	{ 0x1E, 0x00 },

	/* output timing */
	{ 0x1F, 0x3D },//output h total 1792, h active 1366
	{ 0x20, 0x56 },
	{ 0x21, 0x00 },

	{ 0x22, 0x00 },
	{ 0x23, 0x10 },//h sync offset 16
	{ 0x24, 0x60 },//h sync width 96

	{ 0x25, 0x1B },//v active 0x300 = 768
	{ 0x26, 0x00 },
	{ 0x27, 0x1E },//v total 0x31e = 798

	{ 0x28, 0x00 },//output
	{ 0x29, 0x0A },//v sync offset 10
	{ 0x2A, 0x02 },//v sync width 2

//	{ 0x2B, 0x08 },//vga out (8:through scaler)
	{ 0x2B, 0x09 },//vga out (9:bypass scaler)
	{ 0x2C, 0x00 },
	{ 0x2D, 0x00 },
	{ 0x2E, 0x3D },
	{ 0x2F, 0x00 },
	{ 0x32, 0xC0 },
	{ 0x36, 0x40 },//contrast
	{ 0x38, 0x47 },
	{ 0x3D, 0x86 },
	{ 0x3E, 0x00 },
	{ 0x40, 0x0E },
	{ 0x4B, 0x40 },//pwm

//	{ 0x4C, 0xC0 },//lvds output channel order register,bit7:lv_vga_frb bit7: 1 from vga
	{ 0x4C, 0x40 },//lvds output channel order register,bit7:lv_vga_frb
	{ 0x4D, 0x80 },
	/* lvds output timing */
	{ 0x54, 0x80 },//lvds output timing register
	{ 0x55, 0x46 },//lvds output h sync offset 70
	{ 0x56, 0x8F },//lvds output h sync width 143

	{ 0x57, 0x00 },//lvds output 
	{ 0x58, 0x03 },//lvds output v sync offset 3
	{ 0x59, 0x03 },//lvds output v sync width 3

	{ 0x5A, 0x03 },
	{ 0x5B, 0x2A },
	{ 0x5C, 0xAA },
	{ 0x5D, 0xAA },
	{ 0x5E, 0x54 },
	{ 0x60, 0x00 },
	{ 0x61, 0x00 },
	{ 0x64, 0x41 },
	{ 0x68, 0x46 },
	{ 0x6A, 0x41 },
	{ 0x6B, 0x00 },
	{ 0x6C, 0x10 },
	{ 0x6D, 0x00 },
	{ 0x6E, 0xA8 },
	{ 0x70, 0x98 },

	{ 0x74, 0x30 },
	{ 0x75, 0x80 },
	{ 0x7E, 0x0F },//pwm
	{ 0x7F, 0x00 },

	{ 0x03, 0x01 },
	{ 0x08, 0x05 },
	{ 0x09, 0x04 },
	{ 0x0B, 0x65 },
	{ 0x0C, 0x4A },
	{ 0x0D, 0x29 },
	{ 0x0F, 0x9C },
	{ 0x12, 0xD6 },//bit0-5:reserved
	{ 0x13, 0x28 },//non
	{ 0x14, 0x93 },//non
	{ 0x15, 0x00 },//non
	{ 0x16, 0x00 },//non
	{ 0x1A, 0x6C },

	{ 0x1B, 0x00 },//non
	{ 0x1C, 0x00 },
	{ 0x1D, 0x00 },
	{ 0x23, 0x63 },
	{ 0x24, 0xB4 },
	{ 0x28, 0x54 },
	{ 0x29, 0x60 },

	{ 0x41, 0x00 },//lvds control
	{ 0x63, 0x2D },

	{ 0x6B, 0x10 },//non
	{ 0x6C, 0x00 },

	{ 0x03, 0x03 },
	{ 0x26, 0x00 },
	{ 0x28, 0x00 },//output control
	{ 0x2A, 0x00 },

	{ 0x03, 0x04 },
	{ 0x10, 0x01 },
	{ 0x11, 0x4D },
	{ 0x12, 0xFC },
	{ 0x13, 0x02 },
	{ 0x14, 0x88 },
	{ 0x15, 0x70 },
	{ 0x20, 0x14 },
	{ 0x21, 0x20 },
	{ 0x22, 0x00 },
	{ 0x23, 0x00 },
	{ 0x24, 0x20 },
	{ 0x25, 0x00 },
	{ 0x26, 0x40 },
	{ 0x54, 0xC4 },
	{ 0x55, 0x5B },
	{ 0x56, 0x4D },
	{ 0x60, 0x01 },

	{ 0x61, 0x60 },//non
    },
      {//diff: diff with 1024 768 vga datas
      
      //lvds ,in 1024x768,out 1024x768,bypass,mode_idx=8
          { 0x03, 0x04 },
          { 0x52, 0xC3 },
          { 0x5A, 0x06 },
          { 0x5A, 0x04 },
          { 0x5A, 0x06 },
          { 0x52, 0xC1 },
          { 0x52, 0xC3 },
          { 0x5A, 0x04 },
          { 0x03, 0x00 },
          { 0x07, 0xD1 },//diff non
          { 0x08, 0x0F },//diff non
          { 0x09, 0x13 },//bit4: 1 scaler power down
         // { 0x09, 0x03 },//bit4: 0 scaler not power down
          { 0x0A, 0xB6 },//diff bit3: 0 lvds not power down, bit5: 1 mem pwoer down enable bit
         // { 0x0A, 0x96 },//diff bit3: 0 lvds not power down
	//input timing
          { 0x0B, 0x2C },
          { 0x0C, 0x00 },
          { 0x0D, 0x40 },//1024 1344
          { 0x0E, 0x00 },
          { 0x0F, 0x18 },
          { 0x10, 0x88 },//offset 24, width 136
          { 0x11, 0x1B },
          { 0x12, 0x00 },
          { 0x13, 0x26 },//768 806
          { 0x14, 0x00 },
          { 0x15, 0x03 },
          { 0x16, 0x06 },//offset 3, width 6

          { 0x17, 0x00 },
          { 0x18, 0x00 },
	//pix clock
          { 0x19, 0xF8 },
          { 0x1A, 0xFD },
          { 0x1B, 0xE8 },//65000Khz

          { 0x1C, 0x69 },
          { 0x1D, 0x78 },
          { 0x1E, 0x00 },
	//output timing
          { 0x1F, 0x2C },
          { 0x20, 0x00 },
          { 0x21, 0x40 },//1024 1344
          { 0x22, 0x00 },
          { 0x23, 0x10 },
          { 0x24, 0x60 },//16 96
          { 0x25, 0x1B },
          { 0x26, 0x00 },
          { 0x27, 0x26 },//768 806
          { 0x28, 0x00 },
          { 0x29, 0x0A },
          { 0x2A, 0x02 },//10 2

         // { 0x2B, 0x08 },//diff 8:through scaler  9:bypass scaler
          { 0x2B, 0x09 },//diff 8:through scaler  9:bypass scaler
          { 0x2C, 0x00 },
          { 0x2D, 0x00 },
          { 0x2E, 0x3D },
          { 0x2F, 0x00 },
          { 0x32, 0xC0 },
          { 0x36, 0x40 },
          { 0x38, 0x47 },
          { 0x3D, 0x86 },
          { 0x3E, 0x00 },
          { 0x40, 0x0E },
          { 0x4B, 0x40 },
          { 0x4C, 0x40 },//diff2(diff with 1366 768 lvds)
         // { 0x4C, 0xc0 },//diff2(diff with 1366 768 lvds)	//lvds output channel order reg: bit7: 1 lv_vga_frb
          { 0x4D, 0x80 },
	//lvds output timing
          { 0x54, 0x80 },
          { 0x55, 0x18 },
          { 0x56, 0x88 },//offset 24, width 136
          { 0x57, 0x00 },
          { 0x58, 0x03 },
          { 0x59, 0x06 },//offset 3, width 6

          { 0x5A, 0x03 },
          { 0x5B, 0x9C },//diff2 non
          { 0x5C, 0x71 },//diff2 non
          { 0x5D, 0xC7 },//diff2 non
          { 0x5E, 0x54 },
          { 0x60, 0x00 },
          { 0x61, 0x00 },
          { 0x64, 0x2D },//diff2 non
          { 0x68, 0x44 },//diff2 non
          { 0x6A, 0x40 },//diff2 non
          { 0x6B, 0x00 },
          { 0x6C, 0x10 },
          { 0x6D, 0x00 },
          { 0x6E, 0xA0 },//diff2 non
          { 0x70, 0x98 },
          { 0x74, 0x30 },
          { 0x75, 0x80 },
          { 0x7E, 0x0F },
          { 0x7F, 0x00 },
          { 0x03, 0x01 },//page 2
          { 0x08, 0x05 },
          { 0x09, 0x04 },
          { 0x0B, 0x65 },
          { 0x0C, 0x4A },
          { 0x0D, 0x29 },
          { 0x0F, 0x9C },
          { 0x12, 0xD4 },//diff2 bit1: reserved
          { 0x13, 0xA8 },//diff2 non
          { 0x14, 0x93 },//diff non
          { 0x15, 0x00 },
          { 0x16, 0x00 },
          { 0x1A, 0x6C },
          { 0x1B, 0x00 },
          { 0x1C, 0x00 },
          { 0x1D, 0x00 },
          { 0x23, 0x63 },
          { 0x24, 0xB4 },
          { 0x28, 0x54 },
          { 0x29, 0x60 },
          { 0x41, 0x00 },//diff bit6 bit5: h/v sync polarity for lvds. 0 active high, 1 active low
          { 0x63, 0x2D },
          { 0x6B, 0x10 },//diff non 
          { 0x6C, 0x00 },//diff non
          { 0x03, 0x03 },//page 3
          { 0x26, 0x00 },
          { 0x28, 0x00 },//diff bit3 reserved 
          { 0x2A, 0x80 },//diff/diff2 bit7 reserved
          { 0x03, 0x04 },//page 4
          { 0x10, 0x00 },//diff2 bit0 non
          { 0x11, 0xFD },//diff2 non
          { 0x12, 0xE8 },//diff2 non
          { 0x13, 0x02 },
          { 0x14, 0x88 },
          { 0x15, 0x70 },
          { 0x20, 0x14 },//diff non
          { 0x21, 0x20 },//diff non
          { 0x22, 0x00 },
          { 0x23, 0x00 },
          { 0x24, 0x20 },//diff non
          { 0x25, 0x00 },
          { 0x26, 0x40 },//diff non
          { 0x54, 0xC4 },
          { 0x55, 0x5B },
          { 0x56, 0x4D },
          { 0x60, 0x01 },
          { 0x61, 0x62 },//diff2 non
      },
      {
          //1024x768,bypass mode,vga,mode_idx=2, update
          { 0x03, 0x04 },
          { 0x52, 0xC3 },
          { 0x5A, 0x06 },
          { 0x5A, 0x04 },
          { 0x5A, 0x06 },
          { 0x52, 0xC1 },
          { 0x52, 0xC3 },
          { 0x5A, 0x04 },
          { 0x03, 0x00 },
          { 0x07, 0xD9 },//non
          { 0x08, 0xF1 },//non
          { 0x09, 0x13 },//bit4:1 scaler power down
          { 0x0A, 0xBE },//bit3:1 lvds power down
          { 0x0B, 0x2C },
          { 0x0C, 0x00 },
          { 0x0D, 0x40 },
          { 0x0E, 0x00 },
          { 0x0F, 0x18 },
          { 0x10, 0x88 },
          { 0x11, 0x1B },
          { 0x12, 0x00 },
          { 0x13, 0x26 },
          { 0x14, 0x00 },
          { 0x15, 0x03 },
          { 0x16, 0x06 },
          { 0x17, 0x00 },
          { 0x18, 0x00 },
          { 0x19, 0xF8 },
          { 0x1A, 0xFD },
          { 0x1B, 0xE8 },
          { 0x1C, 0x69 },
          { 0x1D, 0x78 },
          { 0x1E, 0x00 },
          { 0x1F, 0x2C },
          { 0x20, 0x00 },
          { 0x21, 0x40 },
          { 0x22, 0x00 },
          { 0x23, 0x10 },
          { 0x24, 0x60 },
          { 0x25, 0x1B },
          { 0x26, 0x00 },
          { 0x27, 0x26 },
          { 0x28, 0x00 },
          { 0x29, 0x0A },
          { 0x2A, 0x02 },
          { 0x2B, 0x09 },
          { 0x2C, 0x00 },
          { 0x2D, 0x00 },
          { 0x2E, 0x3D },
          { 0x2F, 0x00 },
          { 0x32, 0xC0 },
          { 0x36, 0x40 },
          { 0x38, 0x47 },
          { 0x3D, 0x86 },
          { 0x3E, 0x00 },
          { 0x40, 0x0E },
          { 0x4B, 0x40 },
          { 0x4C, 0x40 },
          { 0x4D, 0x80 },
          { 0x54, 0x80 },
          { 0x55, 0x18 },
          { 0x56, 0x88 },
          { 0x57, 0x00 },
          { 0x58, 0x03 },
          { 0x59, 0x06 },
          { 0x5A, 0x03 },
          { 0x5B, 0x9C },
          { 0x5C, 0x71 },
          { 0x5D, 0xC7 },
          { 0x5E, 0x54 },
          { 0x60, 0x00 },
          { 0x61, 0x00 },
          { 0x64, 0x2D },
          { 0x68, 0x44 },
          { 0x6A, 0x40 },
          { 0x6B, 0x00 },
          { 0x6C, 0x10 },
          { 0x6D, 0x00 },
          { 0x6E, 0xA0 },
          { 0x70, 0x98 },
          { 0x74, 0x30 },
          { 0x75, 0x80 },
          { 0x7E, 0x0F },
          { 0x7F, 0x00 },
          { 0x03, 0x01 },
          { 0x08, 0x05 },
          { 0x09, 0x04 },
          { 0x0B, 0x65 },
          { 0x0C, 0x4A },
          { 0x0D, 0x29 },
          { 0x0F, 0x9C },
          { 0x12, 0xD4 },
          { 0x13, 0xA8 },
          { 0x14, 0x83 },
          { 0x15, 0x00 },
          { 0x16, 0x00 },
          { 0x1A, 0x6C },
          { 0x1B, 0x00 },
          { 0x1C, 0x00 },
          { 0x1D, 0x00 },
          { 0x23, 0x63 },
          { 0x24, 0xB4 },
          { 0x28, 0x54 },
          { 0x29, 0x60 },
          { 0x41, 0x60 },
          { 0x63, 0x2D },
          { 0x6B, 0x11 },
          { 0x6C, 0x02 },
          { 0x03, 0x03 },
          { 0x26, 0x00 },
          { 0x28, 0x08 },
          { 0x2A, 0x00 },
          { 0x03, 0x04 },
          { 0x10, 0x00 },
          { 0x11, 0xFD },
          { 0x12, 0xE8 },
          { 0x13, 0x02 },
          { 0x14, 0x88 },
          { 0x15, 0x70 },
          { 0x20, 0x00 },
          { 0x21, 0x00 },
          { 0x22, 0x00 },
          { 0x23, 0x00 },
          { 0x24, 0x00 },
          { 0x25, 0x00 },
          { 0x26, 0x00 },
          { 0x54, 0xC4 },
          { 0x55, 0x5B },
          { 0x56, 0x4D },
          { 0x60, 0x01 },
          { 0x61, 0x62 },
	},
};

#define CH7034_REGMAP_LENGTH_VGA (sizeof(CH7034_VGA_REG_TABLE2[0]) / (2*sizeof(unsigned char)))
#define CH7034_REGMAP_LENGTH_LVDS (sizeof(CH7034_VGA_REG_TABLE2[MODE]) / (2*sizeof(unsigned char)))




void gpioi2c_config_ch7034()
{
	int count;
	unsigned char dev_addr = CHIP_7034_ADDR;
	unsigned char data_addr;
	unsigned char data;
	unsigned char data2;

	unsigned int i;
	unsigned int val_t, val_t2;
	unsigned int hinc_reg, hinca_reg, hincb_reg;
	unsigned int vinc_reg, vinca_reg, vincb_reg;
	unsigned int hdinc_reg, hdinca_reg, hdincb_reg;

	unsigned char id0;
	unsigned char id1;
	unsigned char id2;

	/* get reg base addr */

#if 0	//for vga 800 600
	for (count = 0; count < CH7034_REGMAP_LENGTH_VGA; count++)
	{
		data_addr = CH7034_VGA_REG_TABLE2[0][count][0];
		data = CH7034_VGA_REG_TABLE2[0][count][1];

		gpioi2c_write(dev_addr, data_addr, data);
#if DEBUG_CH7034
		gpioi2c_read(dev_addr, data_addr, &data2);

		if (data != data2)
			printf("not eq, data 0x%2x, data2 0x%2x\n\n\n", data, data2);
#endif
	}
#else	//for lvds 1366 768
#if 1
	for (count = 0; count < CH7034_REGMAP_LENGTH_LVDS; count++)
	{
		/* 0:800 600 vga
		 * 1:1366 768 lvds
		 * 2:1024 768 lvds
		 * 3:1024 768 vga
		 */
		data_addr = CH7034_VGA_REG_TABLE2[MODE][count][0];
		data = CH7034_VGA_REG_TABLE2[MODE][count][1];


		tgt_i2cwrite(I2C_SINGLE,i2caddr,1,data_addr,&data,1);
	}
#endif
		
	data =0;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0xc7,&data,1);
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x1b,&id0,1);
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x1c,&id1,1);
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x1d,&id2,1);


	if (id0 != 0xb0 || id1 != 0x2 || id2 != 0x3) {
		printf("id err\n");
		return;
	}
#if 1

	data =0;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x03,&data,1);
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x25,&i,1);
	data=0x4;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x03,&data,1);

	hinca_reg = (val_t << 3) | (val_t2 & 0x07);
	
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x2a,&val_t,1);
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x2b,&val_t2,1);
	hinca_reg = (val_t << 3) | (val_t2 & 0x07);

	
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x2c,&val_t,1);
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x2d,&val_t2,1);
	hincb_reg = (val_t << 3) | (val_t2 & 0x07);


	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x2e,&val_t,1);
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x2f,&val_t2,1);
	vinca_reg = (val_t << 3) | (val_t2 & 0x07);


	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x30,&val_t,1);
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x31,&val_t2,1);
	vincb_reg = (val_t << 3) | (val_t2 & 0x07);

	

	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x32,&val_t,1);
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x33,&val_t2,1);
	hdinca_reg = (val_t << 3) | (val_t2 & 0x07);


	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x34,&val_t,1);
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x35,&val_t2,1);
	hdincb_reg = (val_t << 3) | (val_t2 & 0x07);
	if (i & (1 << 6)) {
		if (hdincb_reg == 0) {
			printf("dc device error\n");
			return;
		}
		hdinc_reg = (unsigned int)(((unsigned long long)hdinca_reg) * (1 << 20) / hdincb_reg);

		data = (hdinc_reg>>16) &0xff;
		tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x3c,&data,1);
		data = (hdinc_reg >> 8) & 0xff;
		tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x3d,&data,1);
		data =(hdinc_reg >> 0) & 0xff;
		tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x3e,&data,1);
	}
	if (hincb_reg == 0 || vincb_reg == 0) {
		printf("dc device error 2\n");
		return;
	}
	if (hinca_reg > hincb_reg) {
		printf("dc device error 3\n");
		return;
	}

	hinc_reg = (unsigned int)((unsigned long long)hinca_reg * (1 << 20) / hincb_reg);
	vinc_reg = (unsigned int)((unsigned long long)vinca_reg * (1 << 20) / vincb_reg);
	
	data= (hinc_reg >> 16) & 0xff;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x36,&data,1);
	data = (hinc_reg >> 8) & 0xff;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x37,&data,1);
	data = (hinc_reg >> 0) & 0xff;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x38,&data,1);
	data = (vinc_reg >> 16) & 0xff;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x39,&data,1);
	data =(vinc_reg >> 8) & 0xff;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x3a,&data,1);
	data =(vinc_reg >> 0) & 0xff;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x3b,&data,1);
	/* start running */

	data = 0x4;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x3,&data,1);
	data = 0xc7;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x52,&data,1);
	data = 0;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x3,&data,1);



	
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0xa,&val_t,1);
	data = val_t & 0x7f;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0xa,&data,1);

	tgt_i2cread(I2C_SINGLE,i2caddr,1,0xa,&val_t,1);
	data = val_t & 0xef;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0xa,&data,1);
#endif
#endif
}

void gpioi2c_config_sii9022a(void)
{
	unsigned char id0;
	unsigned char id1;
	unsigned char id2;
	unsigned char data;

	unsigned char dev_addr = CHIP_9022_ADDR;

	tgt_printf("gpioi2c_config_sii9022a\n");
//	gpioi2c_init();

#if 1	
	data =0;
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0xc7,&data,1);
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x1b,&id0,1);
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x1c,&id1,1);
	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x1d,&id2,1);

	tgt_printf("id0=0x%x, id1=0x%x, id2=0x%8x\n", id0, id1, id2);

	if (id0 != 0xb0 || id1 != 0x2 || id2 != 0x3) {
		printf("id err\n");
		return;
	}
#endif


	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x1e,&data,1);
	data &= ~(0x3);
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x1e,&data,1);

	tgt_i2cread(I2C_SINGLE,i2caddr,1,0x1a,&data,1);
	data &= ~(1 << 4);
	tgt_i2cwrite(I2C_SINGLE,i2caddr,1,0x1a,&data,1);
}

static const Cmd Cmds[] = {
	{"Misc"},
	{"cfg", "", NULL, "write stream data to a CH7034 chip", gpioi2c_config_ch7034, 1, 5, 0},
	{0, 0}
};

static void init_cmd __P((void)) __attribute__ ((constructor));
static void init_cmd()
{
	cmdlist_expand(Cmds, 1);
}
